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VHDL programming homework help

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Very High-Speed Integrated Circuit Hardware Description Language (VHDL) is a Hardware Description Language (HDL) used by engineers to simulate and describe the functioning of complex digital circuits. It is capable of simulating the structure and behavior of all types of digital systems at multiple abstraction levels. Abstractions in VHDL can range from the simplest such as the system level to the most complex such as logic gates for various programming purposes. Popular examples of VHDL include Pulse Generator, Odd Parity Generator, Behavioral Model and Priority Encoder for 8bit RAM and 16 words. VHDL was standardized by the Institute of Electrical and Electronics Engineers (IEEE) in 1987 as IEEE Standard 1076. It is now commonly used for purposes such as describing hardware, hardware simulation, hardware synthesis, and early performance estimation and assessment of a system architecture.

The latest version of the language provides support for:

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VHDL is used mainly to describe logic circuits by writing textual models. A synthesis program is used to process the model but only when it constitutes the larger logic design. Simulation models created using a simulation program can then be used to test the logic design which represents logic circuits interfacing with the actual design. The set of simulation models used for testing is commonly referred to as a test-bench. VHDL simulators are generally event-driven simulators, meaning that each transaction in the simulation is added to a queue of events scheduled for specified time.

For example, if it is required for a signal assignment to occur after an interval of 1 nanosecond, the event (signal assignment) will be added into the events queue at time+1ns. VHDL also allows for zero delays but the event will still have to be properly scheduled. Delta delay, which represents a time step that is infinitely small, is used in such cases. There are two modes between which the simulation alternates: statement execution wherein evaluations of trigger statements are made; and event processing wherein the queuing and processing of events takes place.

VHDL comes with several inbuilt constructs or processes capable of handling the parallelism which is an integral part of hardware designs. The syntax of those constructs is different from the parallel constructs as seen in other high level programming languages such as Ada. However, VHDL, like Ada, is also a strongly typed language that is not case sensitive. Still, there are many high-end features in VHDL that are lacking in Ada. These include, for example, an extensive set Boolean operators with both “nand” and “nor” that are used to directly represent common hardware operations. With file input and output capabilities, VHDL can be used as an all-purpose text processing language, even though such files are generally used for verification data or stimulus by a simulator test-bench. Some compliers in VHDL are also capable of creating executable binaries. This makes it possible to write a test-bench in the language to verify the viability of design functionality. These test-benches can be written using files located on the host computer which allows for two-way interactions with the user, stimuli defining, and comparisons between the expected and actual results. Most designers however, tend to automate this task by leaving it for the simulator.

Using VHDL makes it relatively easy even for inexperienced programmers to write codes that simulate automatically and accurately, but are impractical due to their very large size. Such codes could also not be synthesized into real devices. One important issue that often comes up while writing a code in VHDL is its proneness to producing transparent latches instead of D-type flip flops as the main elements of storage.

The VHDL integrated development environment allows programmers to design hardware to generate Register-Transfer Logic (RTL) schematic for the required digital circuit. Once the appropriate test-bench has been generated, the schematic generated in the previous step can be verified using simulation software which displays the input and output waveforms of the circuit. It is important that the inputs must be defined accurately in order to generate the correct test-bench for a VHDL code or a specific circuit. For example, an accurate iterative statement or a loop process will be required for a clock input. While translating a VHDL model into a network of wires and gates mapped onto programmable logic devices such as Field Programmable Gate Arrays (FPGA) which are a type of semiconductor devices, the configuration takes place for the actual hardware and not for the VHDL code itself which is being executed.

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Models of the following styles can be created in VHDL:

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Constant: A constant is an object which can be assigned only a single, unchangeable value for the entire duration of the code.

Variable: A variable is also an object which can be assigned only a single value of any type. The difference between a constant and a variable is that while the value a constant object cannot be changed during the code, the value of a variable is changeable. This value can be changed in the course of a simulation using the variable assignment operator (:=)

Signal: A signal object can be declared and defined in the architecture and can be utilized anywhere as the programmer may require within that particular architecture. An assignment operator (<=) is used to assigns signals.


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Aldec is a Henderson, Nevada based software company that sells Electronic Design Automation (EDA) programs. It specializes in verification and simulation solutions and innovative design software that are used in the development of complex Soc, ASIC, FPGA, and other embedded system designs. With a global sales and distribution network spread across 43 countries, more than 50 global partners, and a growing community of over 35,000 active users, Aldec has established itself as a highly regarded provider of design and verification solutions. Since its beginning in 1984, the company has been providing high-end EDA solutions for aerospace, military, government, automotive, telecommunications, and other safety-intensive operations.

Organizations including NASA, GE, IBM, Qualcomm, Texas Instruments, Toshiba, Hewlett Packard, Lockheed Martin, Panasonic, and Samsung use EDA verification suites provided by Aldec to improve performance, reduce costs, and minimize design development cycles.

Main products of the company include:



Operators in VHDL are used to create expressions. Types of operators used in the language are:

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